By Mark Thompson | Published on: January 27, 2014
To start, Let’s go through what a board fabricator needs from an output CAD package briefly and talk about what edits are done at the manufacturing stage. Then discuss why you need to know about them. First, regarding output packages. What does a fabricator need to be able to fab your part?
If the part is Impedance controlled the drawing should describe what lines are being controlled, where they reside and what threshold and tolerance they need to perform at.
Now the fabricator has the job. Are there modifications done to my data for manufacturing? Yes, let’s go through them:
#1 - Drill compensation for plated holes, slots or edge features
Depending upon surface finish fabricators will drill anywhere between .004 and .005 over your specified Finished Hole Size (FHS) to plate back down to your nominal size. Since this is something done by all manufacturers your output data should have already taken this into account. Fabricators like to see a minimum of .002 per side annular ring pad to hole AFTER this drill compensation on signal layers and at least .005-.006 per side pad to copper pour AFTER the drill compensation. Sometimes CAM is a compromise between pad size, drilled hole size, copper weight and available space. Don’t rope yourself into anything if you don’t have to. If the hole is a legitimate VIA and you really don’t care about its Finished hole size make it +.003 minus the entire hole size. This tolerance tells the fabricator it is OK to drill smaller to deal with things like annular ring minimums and can mean the difference between a quote from a fabricator and a “NO BID”.
#2 - Etch Compensations for image data
Depending upon the starting copper, all image data is compensated at the CAM stage to account for the known loss at the fabricators etcher. Typical rule of thumb is a half mil of additional line or metal feature width for every half ounce of starting copper. Exception to the rule is 1/4 oz copper foil where No etch compensation needs to be added. 1/4 oz foils are typically only used for outer or surface layers. Again, your design should be able to accommodate these compensations. (Example: if your design is .003/.003 and you are asking for 2 ounce copper you will get a phone call from your fabricator.)
#3 - Panelization
If you are ordering parts as an array either as a tab rout, score or combination of both you will want to provide a sub panel drawing with any particulars your assembler may need. Additional tooling , fiducials, specific areas where NOT to place a TAB due to part overhang issues at assembly, etc. If you have no preferences and your chosen assembler does not need anything special typically the board fabricator can come up with a good sub panel that works well for both manufacturing and assembly. For instance: Even if no tooling or fiducials are specified for the given array, many times fabricators will add them to the array anyway. They are generally of No Harm at that point and can be quite helpful if tooling and fiducials were not foreseen.
#4 - 1-up compare and Net-list compare
The fabricator will perform a 1-up compare at the CAM stage even if No IPC net-list is provided. This is to ensure the addition of the drill and etch compensations does not create manufacturing capability violations. A 1up compare is ONLY that, It is not a net-list compare. If an IPC 356 file is provided, the fabricator will also run the provided IPC net-list against your provided exported Gerber data. Remember this is a DESIGN vs. Exported Gerber file comparison. If you do not provide an IPC net-list for a Class 3 6012 job your fabricator will ask for one. I have been asked many times over the years to simply, generate a net-list “ based on their exported Gerber data. If a net-list a generated by the fabricator based on the Gerber data at what point would we ever find a mismatch? So what is my point? If you would like us to verify your design iteration against your exported Gerber data please provide an IPC net-list.
Avoid creating test points for things that will be connected only after the devices are loaded such as surface mounts or edge plated castellations. This will avoid a phone call from your fabricator with false or erroneous “broken” or open nets. Likewise many times in a design a AGND to DGND short is designed in, and is intentional. Make note of these intentional net-list anomalies.
Copyright © 2013 Prototron Circuits, Inc. All Rights Reserved.