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Basic Impedance Fabrication Guidelines

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By Mark Thompson | Published on: September 09, 2013

In this post I will talk about co-planar type structures and the effect of unintentional co-planar coupling on Impedances.

What is a “co-planar” structure?

Co-planarity, as it relates to the signal on a PCB is where a portion of metal plane exists on the same layer as the impedance signal and induces some specific amount of coupling due to the proximity of the adjacent plane/copper pour. Often in conjunction with ref planes on adjacent layers these structures offer mechanical and heat sink capabilities greater than those in “free space” or in the case of the PCB, unused non metal areas.

On the other hand, multiple sequential co-planar structures increase the possibility of crosstalk and other unwanted resonance effects, resulting in reduced transmission line performance. An example of unintentional co-planar coupling is when a design is near completion and all details about the outer layer impedances have been worked out. At the last moment the engineer asks for more thermal dispersion or heat sink capabilities and asks the layout person to perform a copper pour on the surface layers to create better thermal capacity and to minimize emissions. Having done so, the fabricator now attempts to model the impedances based on co-planar structures. In some cases, if the impedances are not re-visited after final layout prior to release to the potential fabricator to within 10% of the original intended impedance, you may receive a call from your fabricator regarding subtle re-line sizing to get closer to the intended impedances.

Fig-1
Fig-1 (Click Image to see Larger Version)

Fig-2
Fig-2 (Click Image to see Larger Version)

For many years the “3x rule” has been used and is still valid for most applications today. This is where no copper pour gets any closer to an impedance controlled trace than three times its width. An example would be a .005 line with at least .015 ground separations (distance to adjacent copper pour). Anything less may induce a slight amount of coupling, changing the impedance results up to 5%. In a +/-10% environment. This is a problem for a fabricator.

What do you do? As always I advocate involving the fabricator at the earliest possible time possible before trace layout begins on tight tolerance impedance jobs. Your chosen fabricator should ask at that time whether or not you have any copper pour on any layer closer than 3 x the controlled trace width. Also remember any copper pour added should have the same set – back distance (distance to adjacent copper pour).

Impedance tolerances today are getting tighter requiring greater process controls to be able to achieve the customer’s desired impedances. In addition, some new materials are forcing fabricators to make larger and larger trace and space adjustments to deal with the sometimes large deviation in the available dielectrics on these new material’s, adding in more process variables. Most outer layer impedances today are already at minimum dielectric distances to the ref plane to keep the line and space sizes down for real estate purposes. Add into this close ground coupling and sometimes the necessary modifications result in trace or space values BEYOND the capability of the fabricator.

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